The present invention relates to a semiconductor memory device and a method for arranging memory cells.
FIG. 1 shows a memory cell array 71 including a plurality of (eight shown in FIG. 1) memory cells 72a and 72b that are arranged in accordance with a prior art layout. Two pairs of bit lines (i.e., the first pair being bit line BLA and X bit line XBLA, and the second pair being bit line BLB and X bit line XBLB) connect the memory cells 72a and 72b to one another.
In the prior art memory cell array 71, the memory cell array 71 is configured by a plurality of memory cell units 72. Each memory cell unit 72 includes an even number (e.g., two) of the memory cells 72a and 72b. As shown by the letter F in FIG. 1, adjacent memory cells 72a and 72b are reversed from each other and extend perpendicular to an X axis direction.
Due to the miniaturization of transistors during these recent years, the areas of the memory cells 72a and 72b have been reduced. This has made it difficult to arrange contacts in the memory cells 72a and 72b that are connected with the backgates of transistors.
Japanese Laid-Open Patent Publication No. 8-274271 proposes a solution for solving this problem. As shown in FIG. 2, a non-memory cell region 73 is provided at predetermined intervals in the direction that the bit lines extend (Y axis). In other words, a non-memory cell region 73 is provided for every predetermined number (eight in FIG. 2) of the memory cells 72a and 72b. Backgates are arranged in the non-memory cell region 73.
In the layout of FIG. 2, due to the non-memory cell region 73, the number of bit line contacts differs between the bit line BLA and the X bit line XBLA. The number of bit line contacts also differs between the bit line BLB and the X bit line BLB.
More specifically, in FIG. 2, the number of bit line contacts in each of the bit lines BLA and BLB is six, and the number of bit line contacts in each of the X bit lines XBLA and XBLB is four. As the number of the non-memory cell regions 73 in the memory cell array 71 increases, the difference in the number of bit line contacts between the related bit lines increases.
When the number of bit line contacts differs between the related bit lines, the source-drain capacitance and wire load of the transistor connected to one of the bit lines (in this example, the X bit lines XBLA and XBLB) is greater than the other one of the bit lines (in this example, the bit lines BLA and BLB). Referring to FIG. 3, this results in shortcomings such as the amplitude of bit line signals generated in the X bit lines XBLA and XBLB, which have a relatively large load, being insufficient, and the access time for reading data being long. This problem also occurs when writing data. Thus, in the prior art, reading and writing operations are not performed stably.